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| MOTOROLA SEMICONDUCTOR TECHNICAL DATA Octal 3-State Noninverting Buffer/Line Driver/ Line Receiver with LSTTL-Compatible Inputs High-Performance Silicon-Gate CMOS The MC54/74HCT241A is identical in pinout to the LS241. This device may be used as a level converter for interfacing TTL or NMOS outputs to High-Speed CMOS inputs. The HCT241A is an octal noninverting buffer/line driver/line receiver designed to be used with 3-state memory address drivers, clock drivers, and other bus-oriented systems. The device has non-inverted outputs and two output enables. Enable A is active-low and Enable B is active-high. The HCT241A is similar in function to the HCT244. See also HCT240. * * * * * * Output Drive Capability: 15 LSTTL Loads TTL/NMOS-Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 4.5 to 5.5 V Low Input Current: 1 A In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 118 FETs or 29.5 Equivalent Gates LOGIC DIAGRAM A1 A2 A3 A4 DATA INPUTS B1 B2 B3 B4 11 13 15 17 9 7 5 3 YB1 YB2 2 4 6 8 18 16 14 12 YA1 YA2 YA3 YA4 NONINVERTING OUTPUTS MC54/74HCT241A J SUFFIX CERAMIC PACKAGE CASE 732-03 1 20 20 1 N SUFFIX PLASTIC PACKAGE CASE 738-03 20 1 DW SUFFIX SOIC PACKAGE CASE 751D-04 ORDERING INFORMATION MC54HCTXXXAJ MC74HCTXXXAN MC74HCTXXXADW Ceramic Plastic SOIC PIN ASSIGNMENT ENABLE A A1 YB4 A2 YB3 A3 YB2 A4 YB1 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC ENABLE B YA1 B4 YA2 B3 YA3 B2 YA4 B1 FUNCTION TABLE YB3 YB4 Inputs Enable A L L H Inputs Enable B H H L B L H X A L H X Output YA L H Z Output YB L H Z 1 OUTPUT ENABLE A ENABLES ENABLE B 19 PIN 20 = VCC PIN 10 = GND Z = high impedance X = don't care 2/97 (c) Motorola, Inc. 1997 1 REV 7 MC54/74HCT241A II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I I I I III I I I I I I II I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I I I III I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIII I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I I I I I II I I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIII IIIIIIIIIIIIIIIIIIIIIII I I II I I II I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I III I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIII I I I I II I I I II I II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII II I III I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I III I I I I II II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIII II IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII I I IIII I IIIIIIIIIIIIIIIIIIIIIII III I III I I II I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I IIIIIIIIIIIIIIIIIIIIIII III I I IIIIIIIIIIIIIIIIIIIIIII III II I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIII I I IIIIIIII I I I I IIIIIIIIIIIIIIII III I I I IIIIIIIIIIIIIIIIIIIIIII I I I III I I I IIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIII I I IIIIIIIIIIIIIIIIIIIIIII I I I IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS* Symbol VCC Vin Iin Vout Iout PD Parameter Value Unit V V DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) - 0.5 to + 7.0 - 0.5 to VCC + 0.5 20 35 75 750 500 DC Output Voltage (Referenced to GND) DC Input Current, per Pin - 0.5 to VCC + 0.5III V mA mA mA DC Output Current, per Pin ICC DC Supply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package Storage Temperature mW Tstg TL - 65 to + 150 260 300 _C _C Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) (Ceramic DIP) This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. v v * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). RECOMMENDED OPERATING CONDITIONS Symbol VCC TA Parameter Min 4.5 0 Max 5.5 Unit V V DC Supply Voltage (Referenced to GND) Vin, Vout tr, tf DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time (Figure 1) VCC 500 - 55 0 + 125 _C ns DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol S bl VIH VIL Parameter P Test C di i T Conditions VCC V 4.5 5.5 4.5 5.5 4.5 5.5 4.5 4.5 5.5 4.5 5.5 5.5 - 55 to 25_C 2 2 v 85_C v 125_C 2 2 2 2 0.8 0.8 4.4 5.4 08 0.8 4.4 5.4 3.7 0.1 0.1 0.4 Unit Ui V V V Minimum High-Level Input Voltage Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A Maximum Low-Level Input Voltage VOH Minimum High-Level Output Voltage VOL Maximum Low-Level Output Voltage v Vout = 0.1 V or VCC - 0.1 V |Iout| v 20 A Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL |Iout| v 6 mA Vin = VIH or VIL |Iout| v 20 A Vin = VIH or VIL |Iout| v 6 mA 0.8 0.8 4.4 5.4 3.98 0.1 0.1 3.84 0.1 0.1 V 0.26 0.33 Iin Maximum Input Leakage Current Maximum Three-State Leakage Current IOZ Vin = VCC or GND Output in High-Impedance State Vin = VIL or VIH Vout = VCC or GND Vin = VCC or GND Iout = 0 A 0.1 0.5 1.0 5.0 1.0 10 A A ICC Maximum Quiescent Supply Current (per Package) 5.5 4 40 160 A MOTOROLA 2 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HCT241A I I III I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I II IIIIIII I I I I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII II I I ICC Additional Quiescent Supply Current Vin = 2.4 V, Any One Input Vin = VCC or GND Other Inputs GND, lout = 0 A -55_C 2.9 25_C to 125_C 2.4 5.5 55 mA A NOTES: 1. Information on typical parametric values along with frequency or heavy load considerations can be found in Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). 2. Total Supply Current = ICC + ICC. High-Speed CMOS Logic Data DL129 -- Rev 6 3 MOTOROLA MC54/74HCT241A AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V 10%, CL = 50 pF, Input tr = tf = 6 ns) II I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I II I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I III I I I IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII I III I I I I I II I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIII I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII III III I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I I I I I I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIII IIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIII I Guaranteed Limit Symbol S bl tPLH, tPHL tPLZ, tPHZ tPZL, tPZH Parameter P - 55 to 25_C 23 30 26 12 10 15 v 85_C 29 38 33 15 10 15 v 125_C 35 45 39 18 10 15 Unit Ui ns ns ns ns Maximum Propagation Delay, A to YA or B to YB (Figures 1 and 3) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Propagation Delay, Output Enable to YA or YB (Figures 2 and 4) Maximum Output Transition Time, Any Output (Figures 1 and 3) Maximum Input Capacitance tTLH, tTHL Cin pF pF Cout Maximum Three-State Output Capacitance (Output in High-Impedance State) NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High- Speed CMOS Data Book (DL129/D). Typical @ 25C, VCC = 5.0 V CPD Power Di i i C P Dissipation Capacitance (P E bl d O i (Per Enabled Output)* )* 55 pF F * Used to determine the no-load dynamic power consumption: P D = C PD V CC 2 f + I CC V CC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). SWITCHING WAVEFORMS 3V ENABLE A 1.3 V GND 3V tr INPUT A OR B tPLH OUTPUT YA OR YB tTLH 90% 1.3 V 10% tTHL OUTPUT Y 2.7 V 1.3 V 0.3 V tPHL tf 3V tPZL GND OUTPUT Y 1.3 V 10% tPZH 1.3 V tPHZ 90% tPLZ ENABLE B 1.3 V GND HIGH IMPEDANCE VOL VOH HIGH IMPEDANCE Figure 1. Figure 2. TEST POINT OUTPUT DEVICE UNDER TEST DEVICE UNDER TEST TEST POINT OUTPUT 1 k CONNECT TO VCC WHEN TESTING tPLZ AND tPZL. CONNECT TO GND WHEN TESTING tPHZ AND tPZH. CL* CL* * Includes all probe and jig capacitance * Includes all probe and jig capacitance Figure 3. Test Circuit Figure 4. Test Circuit MOTOROLA 4 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HCT241A LOGIC DETAIL TO THREE OTHER "A" BUFFERS TO THREE OTHER "B" BUFFERS TWO OF 8 BUFFERS INPUT A VCC YA INPUT B VCC YB ENABLE A OUTPUT ENABLES ENABLE B High-Speed CMOS Logic Data DL129 -- Rev 6 5 MOTOROLA MC54/74HCT241A OUTLINE DIMENSIONS J SUFFIX CERAMIC PACKAGE CASE 732-03 ISSUE E B A F C L DIM A B C D F G H J K L M N NOTES: 1. LEADS WITHIN 0.25 (0.010) DIAMETER, TRUE POSITION AT SEATING PLANE, AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSIONS A AND B INCLUDE MENISCUS. MILLIMETERS MIN MAX 23.88 25.15 6.60 7.49 3.81 5.08 0.38 0.56 1.40 1.65 2.54 BSC 0.51 1.27 0.20 0.30 3.18 4.06 7.62 BSC 0_ 15 _ 0.25 1.02 INCHES MIN MAX 0.940 0.990 0.260 0.295 0.150 0.200 0.015 0.022 0.055 0.065 0.100 BSC 0.020 0.050 0.008 0.012 0.125 0.160 0.300 BSC 0_ 15_ 0.010 0.040 20 1 11 10 N H D SEATING PLANE G K J M -A- 20 11 N SUFFIX PLASTIC PACKAGE CASE 738-03 ISSUE E B 1 10 C L NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. INCHES MIN MAX 1.010 1.070 0.240 0.260 0.150 0.180 0.015 0.022 0.050 BSC 0.050 0.070 0.100 BSC 0.008 0.015 0.110 0.140 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 25.66 27.17 6.10 6.60 3.81 4.57 0.39 0.55 1.27 BSC 1.27 1.77 2.54 BSC 0.21 0.38 2.80 3.55 7.62 BSC 0_ 15_ 0.51 1.01 -T- SEATING PLANE K M E G F D 20 PL N J 0.25 (0.010) M 20 PL 0.25 (0.010) TA M M TB M DIM A B C D E F G J K L M N -A- 20 11 DW SUFFIX PLASTIC SOIC PACKAGE CASE 751D-04 ISSUE E 10X -B- 1 10 P 0.010 (0.25) M B M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.150 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 12.65 12.95 7.40 7.60 2.35 2.65 0.35 0.49 0.50 0.90 1.27 BSC 0.25 0.32 0.10 0.25 0_ 7_ 10.05 10.55 0.25 0.75 INCHES MIN MAX 0.499 0.510 0.292 0.299 0.093 0.104 0.014 0.019 0.020 0.035 0.050 BSC 0.010 0.012 0.004 0.009 0_ 7_ 0.395 0.415 0.010 0.029 20X D M 0.010 (0.25) TA S B J S F R X 45 _ C -T- 18X SEATING PLANE G K M MOTOROLA 6 High-Speed CMOS Logic Data DL129 -- Rev 6 MC54/74HCT241A Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado 80217. 303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 81-3-3521-8315 MfaxTM: RMFAX0@email.sps.mot.com - TOUCHTONE 602-244-6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, - US & Canada ONLY 1-800-774-1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 INTERNET: http://www.mot.com/SPS/ High-Speed CMOS Logic Data DL129 -- Rev 6 7 MC74HCT241A/D MOTOROLA |
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